Recent #Memory Technology news in the semiconductor industry
Jülich researchers have introduced novel memristive components in Nature Communications, offering significant advantages over previous versions. These memristors are more robust, operate within a wider voltage range, and can be used in both analog and digital modes. They could address the issue of 'catastrophic forgetting' in artificial neural networks, where learned information is abruptly lost.
The researchers have implemented the new memristive element in a model of artificial neural networks, achieving high accuracy in pattern recognition. They plan to seek further materials for memristors that may perform even better than the current version.
➀ The CXL 3.2 specification has been officially released by the CXL consortium, focusing on optimizing the monitoring and management of CXL memory devices and enhancing their functionality for operating systems and applications.
➁ The specification also extends security through Trusted Security Protocol (TSP) and ensures full backward compatibility with previous CXL specifications.
➂ The CXL technology is designed for high-performance data center servers, allowing processor modules to share memory and providing low-latency interconnect paths for memory access and communication between host processors and devices that need shared memory resources.
➀ The chip industry is striving to increase the stack height of 3D NAND flash memory from 200 layers to 800 layers or more in the coming years to meet the endless demand for various types of memory.
➁ The additional layers will bring new reliability issues and a series of incremental reliability challenges, but the NAND flash memory industry has been steadily increasing the stack height over the past decade.
➂ The development direction of 3D NAND is from 500 to 1,000 layers. However, achieving so many layers is not just a matter of doing more of what we have been doing.
➀ Stanford University is researching a hybrid memory that combines the density of DRAM with the speed of SRAM, funded by CHIPS and Science Act.
➁ The research is part of the California Pacific Northwest AI Hardware Center project, which will receive $16.3 million from the US Department of Defense.
➂ The team, led by H.S. Philip Wong, focuses on developing more energy-efficient hardware for AI, with memory being the core.
➃ The hybrid gain cell memory combines the small footprint of DRAM with the almost as fast speed of SRAM.
➄ The gain cell, similar to DRAM, uses a second transistor instead of a capacitor to store data, with the data stored as charge on the gate of the transistor.
➅ Reading signals are无损 in the gain cell, and the reading transistor provides gain to the storage transistor during reading.
➆ Liu and Wong's mixed gain cell memory, combining silicon read transistors with indium tin oxide write transistors, overcomes limitations and achieves a data retention time of over 5000 seconds.
➇ These hybrid storage cells can be integrated into logic chips, potentially changing the way memory is used in computers.
➀ ReRAM is becoming the preferred alternative to flash memory due to its cost, complexity, power, and performance advantages.
➁ ReRAM is finding its place in power management ICs, IoT, MCU, and edge AI applications.
➂ ReRAM offers inherent security for secure applications and is poised to become a cornerstone for neuromorphic computing.